# dcfifo
# altshift_taps
# a_graycounter
# altsquare
# sld_virtual_jtag
# sld_signaltap
# altstratixii_oct
# altparallel_flash_loader
# altserial_flash_loader
# lpm_constant
# lpm_inv
# lpm_and
# lpm_or
# lpm_xor
# lpm_bustri
# lpm_compare
# lpm_abs
# lpm_counter
# lpm_latch
# lpm_ff
# lpm_shiftreg
# lpm_ram_dq
# lpm_ram_dp
# lpm_ram_io
# lpm_rom
# lpm_fifo
# lpm_fifo_dc
# lpm_inpad
# lpm_outpad
# lpm_bipad
# oper_addsub
# mux21
# io_buf_tri
# io_buf_opdrn
# oper_mult
# tri_bus
# oper_div
# oper_mod
# oper_left_shift
# oper_right_shift
# oper_rotate_left
# oper_rotate_right
# oper_mux
# oper_selector
# oper_decoder
# oper_bus_mux
# oper_latch
# test_bench
# vsim +nowarnTFMPC -L lpm_ver -L sgate_ver -L altera_mf_ver -L altgxb_ver -L stratixiigx_hssi_ver -L stratixgx_ver -L stratixgx_gxb_ver -L stratixiigx -L altera_ver -L stratixiii_ver -L stratixii_ver -L cycloneii_ver -L cycloneiii_ver -t ps test_bench
# // ModelSim ALTERA 6.1g Aug 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.test_bench
# Loading work.nios_ii
# Loading work.button_pio_s1_arbitrator
# Loading work.button_pio
# Loading work.cpu_jtag_debug_module_arbitrator
# Loading work.cpu_data_master_arbitrator
# Loading work.cpu_instruction_master_arbitrator
# Loading work.cpu
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.altsyncram
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_DEVICE_FAMILIES
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_MF_MEMORY_INITIALIZATION
# Loading work.cpu_jtag_debug_module_wrapper
# Loading work.cpu_jtag_debug_module
# Loading work.cpu_mult_cell
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.altmult_add
# Loading work.cpu_test_bench
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate.oper_add
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model.lpm_add_sub
# Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate.oper_less_than
# Loading work.jtag_uart_avalon_jtag_slave_arbitrator
# Loading work.jtag_uart
# Loading work.jtag_uart_scfifo_w
# Loading work.jtag_uart_sim_scfifo_w
# Loading work.jtag_uart_log_module
# Loading work.jtag_uart_scfifo_r
# Loading work.jtag_uart_sim_scfifo_r
# Loading work.jtag_uart_drom_module
# Loading work.ledg_pio_s1_arbitrator
# Loading work.ledg_pio
# Loading work.onchip_mem_s1_arbitrator
# Loading work.onchip_mem
# Loading work.sysid_control_slave_arbitrator
# Loading work.sysid
# Loading work.nios_ii_reset_clk_domain_synch_module
VSIM 3>
Step 2：
显示JTAG UART窗口
输入jtag_uart_drive，printf()的结果将显示在这里
Step 3：
显示waveform window
输入巨集 w 载入wave_presets.do，将载入预设要仿真的信号，也可以自行在加入其他信号。图中的out_port_from_the_ledg_pio就是自行加入的。
Step 4：
开始仿真
输入 run 800 us，表示开始仿真800 us，结果如下图所示。
之前在hello_world.c中，我们曾经
for(i= 0; i< 256; i++)
IOWR_ALTERA_AVALON_PIO_DATA(LEDG_PIO_BASE, i);
若真的在DE2跑起来，只会发现LEDG是全亮的，因为0到255的变化人眼无法辨识，但在ModelSim-Altera就可以看到out_port_from_the_ledg_pio从0、1、2....不断的变化。
结束语
又是一次很神奇的经验，竟然让ModelSim和Nios II结合在一起，这对debug帮助很大，不过ModelSim-Altera与Nios II的整合似乎有待加强，也或许是我功力不足，更复杂的Nios II系统，我也没把握能在ModelSim-Altera仿真成功，毕竟连Nios II Reference Design都过不了，实在令人担心，或许要对Verilog RTL做些修正才能成功仿真。
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本文关键字：暂无联系方式电脑-单片机-自动控制，电子学习 - 基础知识 - 电脑-单片机-自动控制
