--结构体描述部分
ARCHITECTURE bhv OF suocun IS
BEGIN
PROCESS(CLK1HZ) --这里输入的1HZ是来自控制模块的LOAD，LOAD是1HZ的信号
VARIABLE T3,T2,T1,T0 : STD_LOGIC_VECTOR (3 DOWNTO 0);--定义变量
BEGIN
IF RESET = '0' THEN --复位信号为低电平有效，当RESET=0时，将所有值清零
T3 := "0000" ;
T2 := "0000" ;
T1 := "0000" ;
T0 := "0000" ;
ELSIF (CLK1HZ'EVENT AND CLK1HZ='1') THEN --根据题目要求，LOAD上升沿锁存数据
T3:=AIN3;
T2:=AIN2;
T1:=AIN1;
T0:=AIN0;
END IF;
Q3 <= T3;
Q2 <= T2;
Q1 <= T1;
Q0 <= T0;
END PROCESS; --进程结束
END bhv; --结束结构体
最后是译码输出在数码管显示：
-------------------------------------------------------------------
-- 说明: 译码器设计
-- 文件: decoder.vhd
-- 作者:
-- 日期: 2012/04/09
-- 修改:
-- 软件: Altera QuartusII 9.0
-- 芯片: Altera Cyclone FPGA (EP1C3T144C8)
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder IS
PORT(
ain : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
yout : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END decoder;
ARCHITECTURE yimaqi OF decoder IS
BEGIN
PROCESS ( ain )
BEGIN
CASE ain IS
WHEN "0000" => yout<= "0111111"; --0
WHEN "0001" => yout<= "0000110"; --1
WHEN "0010" => yout<= "1011011"; --2
WHEN "0011" => yout<= "1001111"; --3
WHEN "0100" => yout<= "1100110"; --4
WHEN "0101" => yout<= "1101101"; --5
WHEN "0110" => yout<= "1111101"; --6
WHEN "0111" => yout<= "0000111"; --7
WHEN "1000" => yout<= "1111111"; --8
WHEN "1001" => yout<= "1101111"; --9
WHEN "1010" => yout<= "1110111"; --A
WHEN "1011" => yout<= "1111100"; --B
WHEN "1100" => yout<= "0111001"; --C
WHEN "1101" => yout<= "1011110"; --D
WHEN "1110" => yout<= "1111001"; --E
WHEN "1111" => yout<= "1110001"; --F
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END yimaqi;
本文关键字：设计程序 源码-程序，单片机-工控设备 - 源码-程序
