VHLD实例最高优先级编码器 8位相等比较器

library IEEE;   
use IEEE.Std_logIC_1164.all;

entity HCT245 is
   port(A, B : inout std_logic_vector(7 downto 0);
         DIR, GBAR : in std_logic);
end HCT245;

architecture VER1 of HCT245 is
begin
   A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');
   B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');
end VER1;

本文关键字：编码器  优先级  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术