VHLD实例二进制到格雷码转换

--
--
------------------------------------------------------------------------------------
-- DESCRIPTION   :  Bin to gray converter
--                  Input (DATA_IN) width : 4
--                  Enable (EN) active : high

-- Download from :  http://www.pld.com.cn
------------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logIC_1164.all;

entity BIN2GARY is
	port (
		DATA_IN : in std_logic_vector (3 downto 0);
		EN : in  std_logic;
		DATA_OUT : out std_logic_vector (3 downto 0)
	);
end entity;


architecture bin2gary_arch of BIN2GARY is
begin

	DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;
	DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
	DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
	DATA_OUT(3) <= DATA_IN(3) and EN;

end architecture;

本文关键字：二进制  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术