/* ADC0CN 0xE8 */
sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
sbit AD0INT = ADC0CN ^ 5; /* ADC 0 EOC INTERRUPT FLAG */
sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 CONVERT START MODE BIT 1 */
sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 CONVERT START MODE BIT 0 */
sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW INTERRUPT FLAG */
/* ADC2CN 0xE8 */
sbit AD2EN = ADC2CN ^ 7; /* ADC 2 ENABLE */
sbit AD2TM = ADC2CN ^ 6; /* ADC 2 TRACK MODE */
sbit AD2INT = ADC2CN ^ 5; /* ADC 2 EOC INTERRUPT FLAG */
sbit AD2BUSY = ADC2CN ^ 4; /* ADC 2 BUSY FLAG */
sbit AD2WINT = ADC2CN ^ 3; /* ADC 2 WINDOW INTERRUPT FLAG */
sbit AD2CM2 = ADC2CN ^ 2; /* ADC 2 CONVERT START MODE BIT 2 */
sbit AD2CM1 = ADC2CN ^ 1; /* ADC 2 CONVERT START MODE BIT 1 */
sbit AD2CM0 = ADC2CN ^ 0; /* ADC 2 CONVERT START MODE BIT 0 */
/* SPI0CN 0xF8 */
sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
sbit NSSMD1 = SPI0CN ^ 3; /* SPI 0 SLAVE SELECT MODE BIT 1 */
sbit NSSMD0 = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT MODE BIT 0 */
sbit TXBMT = SPI0CN ^ 1; /* SPI 0 TX BUFFER EMPTY */
sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
/* CAN0CN 0xF8 */
sbit CANINIT = CAN0CN ^ 0; /* CAN Initialization bit */
sbit CANIE = CAN0CN ^ 1; /* CAN Module Interrupt Enable Bit */
sbit CANSIE = CAN0CN ^ 2; /* CAN Status change Interrupt Enable Bit */
sbit CANEIE = CAN0CN ^ 3; /* CAN Module Error Interrupt Enable Bit */
sbit CANIF = CAN0CN ^ 4; /* CAN Module Interrupt Flag */
sbit CANDAR = CAN0CN ^ 5; /* CAN DISAble Automatic Retransmission bit */
sbit CANCCE = CAN0CN ^ 6; /* CAN Configuration Change Enable bit */
sbit CANTEST = CAN0CN ^ 7; /* CAN Test Mode Enable bit */
/* SFR PAGE DEFINITIONS */
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
#define CPT2_PAGE 0x03 /* COMPARATOR 2 */
#define UART0_PAGE 0x00 /* UART 0 */
#define UART1_PAGE 0x01 /* UART 1 */
#define SPI0_PAGE 0x00 /* SPI 0 */
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
#define ADC0_PAGE 0x00 /* ADC 0 */
#define ADC2_PAGE 0x02 /* ADC 2 */
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