Verilog HDL 实例设计程序双向管脚（clocked bidirectional pin）

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input   oe;
input   clk;
input   [7:0] inp;
output  [7:0] outp;
inout   [7:0] bidir;

reg     [7:0] a;
reg     [7:0] b;

assign bidir = oe ? a : 8'bZ ;
assign outp  = b;

// Always Construct

always @ (posedge clk)
begin
	b <= bidir;
	a <= inp;
end

endmodule

本文关键字：设计程序  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术