摘要：本文比较了DS26303和IDT82V2048的不同，特别说明了如何在已有的IDT82V2048应用中使用DS26303，详细阐述了它们的特性区别、寄存器和硬件设计时的考虑。
概述
本文比较了DS26303和IDT82V2048的不同，特别阐述了如何在已有的IDT82V2048应用中使用DS26303。DS26303是一个单3.3V供电的8通道E1/T1/J1短程线路接口单元(LIU)。不需要更改软件就可以支持IDT82V2048的功能，并提供附加的特性。不需要改变PCB，DS26303就可以用在现有的IDT82V2048应用中，仅仅需要根据应用改变外围元器件值。
特性的区别分为三个不同部分：表1为DS26303具备而IDT82V2048不具备的一些特性；表2为IDT82V2048具备而DS26303不具备的一些特性。表3为DS26303和IDT82V2048共有但是在两个器件上实现不同的特性。
表6到表10为DS26303和IDT82V2048寄存器之间的不同以及DS26303附加寄存器组提供的附加功能。图1和表11为在现有的IDT82V2048应用中使用DS26303时需要对器件值所做的细微改变。
表1. DS26303不同于IDT82V2048的特性 DS26303IDT82V2048Programmable option to clear interrupt status on write or read. Clear on read is default.Not supported.Individual channel control for jitter attenuator:
- Enable/disable
- FIFO depth
- FIFO limit trip
All channels have global control.Internal software-selectable transmit and receive-side termination for 100Ω T1 twisted-pair, 110Ω J1 twisted-pair, 120Ω E1 twisted-pair, and 75Ω E1 coaxial applications.Not supported.In HPS mode, the transmitter output and the internal impedance of the receiver can be turned off with only the OE pin.Requires that both receivers use the same front-end termination.Built in BERT tester for diagnostics.Not supported.Individual channel control for:
- Short-circuit protection
- AIS enable on LOS
- RCLK inversion
- TCLK inversion
All channels have global control.Individual channel-line violation detection.Not supported.Flexible MCLK See Table 4 for available input frequencies.Not supported.Programmable TECLK output pin (1.544MHz or 2.048MHz)Not supported.Programmable CLKA output pin See Table 5 for available output frequencies.Not supported.Flexible interrupt pinNot supported.
表2. IDT82V2048不同于DS26303的特性 DS26303IDT82V2048Uses single optimal value.Capability to select the jitter attenuator bandwidth.Not provided.Inband loopack (loopup and loopdown codes).MLCK Pin Functionality
The DS26303 and IDT82V2048 both require MCLK to for data with clock recovery as well as AIS detection.
The MCLK pin of the IDT82V2048 provides additional functionality not present in the DS26303.
IDT82V2048 MCLK held high.
- The IDT82V2048 slices the incoming bipolar line signal into RZ pulse (data-recovery mode).
IDT82V2048 MCLK held low.
- All the receivers are powered down, and the output pins RCLKn, RDPn, and RDNn are switched to high impedance.
Note that wait state generation through RDY/ACK is not available if MCLK is not provided.
表3. DS26303和IDT82V2048的特性区别 DS26303IDT82V20483.3V LIU power only, 5V not provided.5V LIU power.Non-mux Intel® write address to WRB rising-edge setup time is 17ns.Non-mux Intel write address to WRB rising-edge setup time is 6ns.Expects non-mux Intel read address to be valid when RDB is active.Non-mux Intel read address to RDB rising-edge setup time is 6ns. This might be an error in data sheet because data is out before this setup time.Inactive RDY to tri-state delay time 12ns (max).Inactive RDY to tri-state delay time 3ns (max).Clears the interrupt pin when reading or writing the interrupt status.Clear interrupt pin by reading the corresponding status register.Jitter attenuator FIFO depths of 32 bits or 128 bits.Jitter attenuator FIFO depths of 32 bits or 64 bits.Individual channel control for jitter attenuator:
- Enable/disable
- FIFO depth
- FIFO limit trip
All channels have global control.
表4. DS26303 MCLK的选择范围 PLLEMPS1, MPS0MCLK MHz (±50ppm)FREQST1 or E1 Mode0xx1.544xT10xx2.048xE11001.5441T1/J1 or E11013.0881T1/J1 or E11106.1761T1/J1 or E111112.3521T1/J1 or E11002.0480T1/J1 or E11014.0960T1/J1 or E11108.1920T1/J1 or E111116.3840T1/J1 or E1
表5. DS26303时钟A的选择范围 CLKA3 to CLKA0MCLK (Hz)00002.048M00014.096M00108.192M001116.384M01001.544M01013.088M01106.176M011112.352M10001.536M10013.072M10106.144M101112.288M110032k110164k1110128k1111256k
寄存器的考虑事项
DS26303包括四个主要的寄存器组。
- 主寄存器组(DS26303和IDT82V2048)
- 二级寄存器组(DS26303和IDT82V2048)
- 独立LIU寄存器组(DS26303独有)
- BERT寄存器组(DS26303独有)
为了利用DS26303的附加特性和灵活性，必须在IDT82V2048应用的源代码中添加程序。地址指针控制寄存器(ADDP)的地址为1Fh，它被用作指针来访问不同的寄存器组。表6给出了DS26303寄存器组列表和访问这些寄存器组时所需要的ADDP值。
表6. DS26303地址指针选择 ADDP7 to ADDP0 (Hex)Bank NameDS26303IDT82V204800Primary BankYesYesAASecondary BankYesYes01Individual LIU BankYesNo02BERT BankYesNo
DS26303的主寄存器组和IDT82V2048是一样的。如果使用DS26303替换现有的IDT82V2048，并且仅用到主寄存器组，则不需要修改应用软件。表7给出了主寄存器组列表。
表7. DS26303和IDT82V2048的主寄存器组 Address (Hex)DS26303 and IDT82V204800–15Primary Registers16–1EReserved1FADDP
尽管DS26303与IDT82V2048都提供二级寄存器组，但并不是所有寄存器及其相应功能都是一样的。表8给出了二级寄存器组包含的寄存器列表，以及它们在DS26303和IDT82V2048中实现的功能。
DS26303包含另外两个寄存器组：独立LIU寄存器组和BERT寄存器组。表9为独立LIU寄存器组包含的寄存器列表，表10为BERT寄存器组包含的寄存器列表。为了利用DS26303的附加特性和灵活性，必须在IDT82V2048应用的源代码中添加程序。
表8. DS26303的二级寄存器组 Address (Hex)Register NameDS26303IDT82V204800Single-Rail Mode SelectYesYes01Line-Code SelectionYesYes02Clock-Recovery EnableNoYes03Receiver Power-Down EnableYesYes04Transmitter Power-Down EnableYesYes05Excessive Zero-Detect EnableYesYes06Code-Violation-Detect Enable BarYesYes07Receive Equalizer EnableNoYes08Inband Loopback (LB) ConfigurationNoYes09Inband LB Activation CodeNoYes0AInband LB Deactivation CodeNoYes0BInband LB Receive StatusNoYes0CInband LB Interrupt MaskNoYes0DInband LB Interrupt StatusNoYes0EInband LB Activation/Deactivation Code GeneratorNoYes1FSet to AAh for access to Secondary Register BankYesYes
表9. DS26303的独立LIU寄存器组 Address (Hex)Register Name00Individual JA Enable 01Individual JA POSTTTION Select02Individual JA FIFO Depth Select03Individual JA FIFO Limit Trip04Individual Short-Circuit Protection Disable05Individual AIS Select06Master-Clock Select07Global-Management Register08–0FReserved10Bit-Error-Rate Tester Control Register12Line-Violation Detect Status13Receive-Clock Invert14Transmit-Clock Invert15Clock-Control Register16RCLK Disable Upon LOS Register1EGlobal-Interrupt Status Control1FSet to 01h for access to Individual LIU Register Bank
表10. DS26303的BERT寄存器组 Address (Hex)Register Name00BERT Control Register01Reserved02BERT Pattern Configuration 103BERT Pattern Configuration 204BERT Seed/Pattern 105BERT Seed/Pattern 206BERT Seed/Pattern 307BERT Seed/Pattern 408Transmit-Error Insertion Control09–0AReserved0CBERT Status Register0DReserved0EBERT Status Register Latched10BERT Status Register Interrupt Enable11–13Reserved14Receive Bit-Error Count Register 115Receive Bit-Error Count Register 216Receive Bit-Error Count Register 317Receive Bit-Error Count Register 418Receive Bit-Count Register 119Receive Bit-Count Register 21AReceive Bit-Count Register 31BReceive Bit-Count Register 41C–1EReserved1FSet to 02h for access to BERT Register Bank
硬件考虑事项
不用改变PCB就可以用DS26303替换现有应用中的IDT82V2048。需要做的是根据目标应用改变外部器件值。图1为DS26303推荐的网络端接电路，表11为DS26303正确端接时需要的器件值。
发送器
IDT82V2048要求发送端电阻串联接入TTIP和TRING输出，建议这些电阻应该为0Ω (T1 3.3V模式)，9.5Ω (E1 75Ω同轴)或者9.1Ω (E1 120Ω双绞线)。DS26303不要求电阻，所以所有模式中的电阻都应该为0Ω。
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本文关键字：接口 电力配电知识，电工技术 - 电力配电知识
