FPGA学习Verilog HDL实验－－-小项目2同步时序电路设计

ICP;

oR1;

oY1;

oG1;

oR2;

oY2;

oG2;

oR1;

oY1;

oG1;

oR2;

oY2;

oG2;

[5:0] time1;

[5:0] time2;

[1:0] state;

oR1 <= 1'b1;

oY1 <= 1'b0;

oG1 <= 1'b0;

oR2 <= 1'b0;

oY2 <= 1'b0;

oG2 <= 1'b1;

time1 <= 6'd15;

time2 <= 6'd10;

state <= 2'b00;

@(iCP)

(state)

2'b00://S1

time1 = time1 - 6'd1;

(time1 != 6'd3)//H: R1--1

//V: G2--1

state <= state;

oR1 <= 1'b1;

oY1 <= 1'b0;

oG1 <= 1'b0;

oR2 <= 1'b0;

oY2 <= 1'b0;

oG2 <= 1'b1;

//H: R1--1

//V: Y2--1

state <= 2'b01;

oR1 <= 1'b1;

oY1 <= 1'b0;

oG1 <= 1'b0;

oR2 <= 1'b0;

oY2 <= 1'b1;

oG2 <= 1'b0;

2'b01://S2//H: R1--1

//V: Y2--1

time1 = time1 - 6'd1;

(time1 != 6'd0)

state <= state;

oR1 <= 1'b1;

oY1 <= 1'b0;

oG1 <= 1'b0;

oR2 <= 1'b0;

oY2 <= 1'b1;

oG2 <= 1'b0;

//H: G1--1

//V: R2--1

state <= 2'b10;

time1 <= 6'd15;

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本文关键字：小项目  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术