Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. All FM receivers incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two time constants, 50 or 75 μs, are used in various regions.
The de-emphasis time constant is programmable with the DE bit. High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins.
The audio output may be muted with the DMUTE bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be set to either –28 dBFS (default) or –58 dBFS by setting VOLEXT=1.
The soft mute feature is available to attenuate the audio outputs and minimize audible noise in weak signal conditions. The soft mute attack and decay rate can be adjusted with the SMUTER[1:0] bits where 00 is the fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the most attenuated. The soft mute disable (DSMUTE) bit may be set high to disable this feature.
Tuning
The Si4702/03-C19 uses Silicon Laboratories’ patented and proven frequency synthesizer technology including a completely integrated VCO. The frequency synthesizer generates the quadrature local oscillator signal used to downconvert the RF input to a low intermediate frequency. The VCO frequency is locked to the reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception. The tuning frequency is defined as:
Channel spacing of 50, 100 or 200 kHz is selected with bits SPACE[1:0]. The channel is selected with bits CHAN[9:0]. Band selection for Japan, Japan wideband, or Europe/U.S./Asia is set with BAND[1:0]. The tuning operation begins by setting the TUNE bit. After tuning completes, the seek/tune complete (STC) bit will be set and the RSSI level is available by reading bits RSSI[7:0]. The TUNE bit must be set low after the STC bit is set high in order to complete the tune operation
and clear the STC bit.
Seek tuning searches up or down for a channel with an RSSI greater than or equal to the seek threshold set with the SEEKTH[7:0] bits. In addition, optional SNR and/or impulse noise detector criteria may be used to qualify valid stations. The SKSNR[3:0] bits set the SNR threshold required. The SKCNT[3:0] bits set the impulse noise threshold. Using the extra seek qualifiers can reduce false stops and, in combination with lowering the RSSI seek threshold, increase the number of found stations. The SNR and impulse noise detectors are disabled by default for backwards compatibility.
Two seek modes are available. When the seek mode (SKMODE) bit is low and a seek is initiated, the device seeks through the band, wraps from one band edge to the other, and continues seeking. If the seek operation is unable to find a valid channel, the seek failure/band limit (SF/BL) bit is set high and the device returns to the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated, the device seeks through the band until the band limit is reached and the SF/BL bit is set high. A seek operation is initiated by setting the SEEK and SEEKUP bits. After the seek operation completes, the STC bit is set, and the RSSI level and tuned channel are available by reading bits RSSI[7:0] and bits READCHAN[9:0]. During
a seek operation READCHAN[9:0] is also updated and may be read to determine and report seek progress. The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and the SF/BL bit is set low. At other times, such as before a seek operation or after a seek completes and the SF/BL bit is set high, the channel is valid if the AFC Rail (AFCRL) bit is set low and the value of RSSI[7:0] is greater than or equal to SEEKTH[7:0]. Note that if a valid channel is found but the AFCRL bit is set, the audio output is muted as in the softmute case discussed in Section “4.5. Stereo Audio Processing”. The SEEK bit must be set low after the STC bit is set high in order to complete the seek operation. Setting the STC bit low clears STC status and SF/BL bits. The seek operation may be aborted by setting the SEEK bit low at any time.
The device can be configured to generate an interrupt on GPIO2 when a tune or seek operation completes. Setting the seek/tune complete (STCIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low interrupt when the STC bit is set by the device.
Reference Clock
The Si4702/03-C19 accepts a 32.768 kHz reference clock to the RCLK pin. The reference clock is required whenever the ENABLE bit is set high. Refer to Table 3, “DC Characteristics1,” on page 5 for input switching voltage levels and Table 8, FM Receiver Characteristics, on page 12 for frequency tolerance information.
An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to 2. Typical Application Schematic on page 14. The oscillator must be enabled or disabled while in powerdown (ENABLE = 0) as shown in Figure 9, “Initialization Sequence,” on page 21. Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown. Note that RCLK voltage levels are not specified. The typical RCLK voltage level, when the crystal oscillator is used, is 0.3 Vpk-pk.
Si4702/03-C19 Internal Crystal Oscillator Errata
The Si4702/03-C19 seek/tune performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4702/03-C19 is performing the seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops. SDIO activity during all other operational states does not affect performance.
For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4702/03-C19 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The STC (seek/tune complete) interrupt should be used instead of polling to determine when a seek/tune operation is complete.
The layout guidelines in Si4700/01/02/03 Evaluation Board User’s Guide, Section 8.3 Si4702/03-C19 Daughter Card should be followed to help ensure robust FM performance.
Please refer to the posted Si4702/03 Internal Crystal Oscillator Errata for more information.
Control Interface
Two-wire slave-transceiver and three-wire interfaces are provided for the controller IC to read and write the control registers. Refer to “4.9. Reset, Powerup, and Powerdown” for a deSCRJPTion of bus mode selection. Registers may be written and read when the VIO supply is applied regardless of the state of the VD or VA supplies. RCLK is not required for proper register operation.
3-Wire Control Interface
For three-wire operation, a transfer begins when the SEN pin is sampled low by the device on a rising SCLK edge. The control word is latched internally on rising SCLK edges and is nine bits in length, comprised of a four bit chip address A7:A4 = 0110b, a read/write bit (write = 0 and read = 1), and a four bit register address, A3:A0. The ordering of the control word is A7:A5, R/W, A4:A0. Refer to Section 5. Register Summary on page 22 for a list of all registers and their addresses.
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